Method and apparatus  for memory command input and control

ABSTRACT

Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also prevent coupling commands to the interconnect bus based on the receipt of chip select signals having inactive states. Chip enable circuits having control logic are configured to receive chip select signals and provide the chip select signals to an interconnect bus responsive to receiving a valid command. Chip enable circuits may also prevent coupling chip select signals to the interconnect bus from chip enable signals based on the receipt of invalid command signals. Signal truncation circuits may be used to shorten and/or shift chip select signals to increase timing margins and improve the reliability of command execution by memories.

CROSS REFERENCE TO RELATED APPLICATION(S)

This application is a continuation of pending U.S. patent application Ser. No. 13/168,723, filed Jun. 24, 2011 which application is incorporated herein by reference, in its entirety, for any purpose.

TECHNICAL FIELD

This invention relates to memory systems, and more particularly, to memory systems using a master-slave configuration in memory.

BACKGROUND OF THE INVENTION

As memory devices of all types have evolved, continuous strides have been made in improving their performance in a variety of respects. For example, to further efforts of maximizing storage density, multiple memories have been placed together into a single package. Such implementations increase the storage space in memory while reducing the overall physical footprint. In some designs, only one memory of a package is linked to external devices through the packaging substrate. Thus capacitive loading of a multiple memory package is equivalent to that of a single memory package. Moreover, one memory is often connected to the package I/O (i.e. “master”) and configured to interface with other memories (i.e. “slaves”) via memory to memory interconnections. As a result, proper operation of the memory communication requires routing command signals to the correct memory within the package and relies on various internal clock and control signals as well as the timing of those signals relative to one another.

Because master memory control logic interfacing with external devices is normally synchronous, the execution of logic functions must occur within a certain amount of time, typically equal to the clock period. As the external clock and control signal frequencies are increased, inherent timing variations between internal signals of the system relative to one another become more significant. Thus, maintaining correct signal timing between various command signals has presented difficulties in high frequency systems. Signal propagation delays can fluctuate due to variations in logic gate delay and electrical characteristics of memory to memory interconnections, and if relative timing is not maintained, erroneous operation may occur, resulting, for example, in a memory registering improper command instructions. Additionally, signal skewing may become even further pronounced for systems consisting of multiple components that work in coordination for proper operation. Accordingly, there is therefore a need for memory logic that can reduce timing variation dependency in multiple device memories utilizing high clock frequencies.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a memory according to an embodiment of the invention.

FIG. 2 is a block diagram of a portion of a memory unit included in the memory of FIG. 1 according to an embodiment of the invention.

FIG. 3 is a block diagram of a command latch decoder for a memory unit according to an embodiment of the invention.

FIG. 4 is a block diagram of a chip enable circuit for a memory unit according to an embodiment of the invention.

FIGS. 5A and 5B are diagrams of control logic tables according to embodiments of the invention.

FIG. 6 is a timing diagram of various signals during memory operation according to an embodiment of the invention.

FIG. 7 is a circuit diagram of a chip enable circuit for a memory unit according to an embodiment of the invention.

FIG. 8 is a front perspective view of a memory according to an embodiment of the invention.

DETAILED DESCRIPTION

Embodiments of the invention are directed toward a memory having a master-slave memory unit configuration that provides decoding logic for memory control bus implementations. Certain details are set forth below to provide a sufficient understanding of various embodiments of the invention. However, it will be clear to one skilled in the art that the invention may be practiced without these particular details. In other instances, well-known circuits, control signals, and timing protocols have not been shown in detail in order to avoid unnecessarily obscuring the invention.

FIG. 1 illustrates a memory 100 according to an embodiment of the present invention. The memory 100 may include a master memory unit 102 and a plurality of slave memory units 104 a-c. The master memory unit 102 and each of the plurality of slave memory units 104 a-c may be identical and may be stacked on top of each other. Additionally, memory units included in the memory 100 may be on a common substrate or multi-chip module. Although the memory 100 includes four memory units, other embodiments may include a lesser or greater number of memory units. Memory units in memory unit 100 may include an array of memory cells and control logic for accessing data stored in the memory arrays.

An interconnect bus 110 included in memory 100 may allow master memory unit 102 to interface with the plurality of slave memory units 104 a-c. Interconnect bus 110 may include a plurality of signal lines configured for enabling a particular memory unit during a memory command and/or transmitting commands to memory units to execute. Such commands may include, for example, read, write, precharge, and refresh operations. Master memory unit 102 may further be coupled to slave memory units 104 a-c through a read bus 112 and a write bus 114 on which data may be exchanged. Interconnect bus 110, read bus 112, and write bus 114 may be implemented with interconnects, such as wires, conductive structures, or through silicon vias (“TSVs”) used to interconnect stacked die.

Memory 100 also may include an I/O bus 108 through which sequential input/output (“I/O”) signals associated with conventional memory commands, addresses, and write data are applied to master memory unit 102. Similarly, I/O signals corresponding to read data may be read out of master memory unit 102 through I/O bus 108. Each signal line associated with I/O bus 108 may be coupled to a corresponding contacts 150. Contacts 150 may act as an external nodes for memory 100 and allow data to be exchanged between memory 100 and an external device (not shown).

Master memory unit 102 may also include control logic for receiving signals over I/O bus 108. In at least one embodiment, for example, such signals may include a row address select signal RAS#, a column address select signal CAS#, a write enable signal WE#, a clock signal CLK, and a plurality of chip select signals (e.g. CS0#-CS3#). While command signals received by memory 100 may be active low signals, other embodiments may utilize other methods as will be appreciated by those skilled in the art.

Each of the chip select signals may correspond to the master memory unit 102 and the plurality of slave memory units 104 a-c. For example, chip select signal CS0# may correspond to master memory unit 102, CS1# may correspond to slave memory unit 104 a, etc. It will be appreciated by those skilled in the art that although the embodiment in FIG. 1 includes a total of three slave memory units 104, any number of slave memory units 104 and corresponding chip select signals may be implemented in memory 100.

In operation, a command is provided through contacts 150 to the master memory unit 102. Control logic inside of the master memory unit 102 decodes the command and determines if either the master memory unit 102 or any of the plurality of slave memory units 104 a-c is intended to receive the decoded command. Specifically, chip select signals are processed to determine if any memory unit in memory 100 should be enabled based on an active state chip select signal corresponding to a specific memory unit. Master memory unit 102 may also decode other signals to determine the type of command received. RAS#, CAS#, and WE#, for example, may be decoded to determine the type of command to be executed on an enabled memory unit.

As will be explained in greater detail below, if a chip select signal has an active state and the decoded command is valid, the command may be coupled to the interconnect bus 110 and the memory unit corresponding to the active state chip select signal may be enabled to read the command from of the interconnect bus 110 and execute the command accordingly.

In some embodiments, interconnect bus 110 may have a width of 11 bits with seven bits corresponding to a command set and four bits corresponding to each memory unit in a four memory unit system. It will be appreciated by one skilled in the art that interconnect bus 110 may have any bit width and that other embodiments may implement any number of memory units.

A master memory unit 102 and a plurality of slave memory units 104 a-c according to an example of the invention are shown in FIG. 2. The master memory unit 102 includes an input path circuit 202 configured to receive command signals over I/O bus 108 (FIG. 1). In an embodiment, input path 202 is configured to receive a row address select signal, a column address select signal, a write enable signal, and a plurality of chip select signals (FIG. 1) on the I/O bus 108. Input path circuit 202 may further include control logic to generate inverted signals corresponding to those received on I/O bus 108. The design and operation of such logic is well known by those ordinarily skilled in the art, and consequently, a more detailed description has been omitted from herein in the interest of brevity.

Input path circuit 202 may interface with a plurality of chip enable circuits 206 through chip enable busses 205. A corresponding chip enable circuit 206 may be included in master memory unit 102 for each chip select input included in I/O bus 108. Chip enable busses 205 may be configured to couple row address select signals, column address select signals, and write enable signals to each chip enable circuit 206. Chip enable busses 205 may be further configured to couple each chip select signal from input path 202 to the corresponding chip enable circuit 206.

Input path 202 may further interface with command latch decoder 204 over local command bus 203. Command latch decoder 204 may contain control logic for decoding commands received by input path 202 and detecting if any chip select signals are in an active state. As will be explained further below, this ensures that commands reach interconnect bus 110 only when one of the memory units has an active corresponding chip select signal.

Both command latch decoder 204 and chip enable circuits 206 may further be coupled to a master interconnect 208 over a global command bus 207 and a latched chip select bus 209, respectively. This allows for both active chip select signals and decoded commands to be coupled to master interconnect 208. As will be explained below in greater detail, active chip select signals and valid decoded commands may be coupled to the interconnect bus 110 from master interconnect 208 and subsequently to a specific memory unit in memory 100.

Slave memory units 104 a-c included in memory 100 (FIG. 1) are also illustrated in FIG. 2. Each slave memory unit 104 includes a slave interconnect 210 that is coupled to the interconnect bus 110. As interconnect bus 110 is further coupled to master interconnect 208, commands and active chip select signals may be coupled from the master memory unit 102 to the slave memory units 104 a-c via interconnect bus 110.

In operation, command signals are coupled from the contacts 150 (FIG. 1) to the input path 202. The signals received by input path 202 are then coupled to both the command latch decoder 204 and the chip enable circuits 206. Command latch decoder 204 may receive command signals RAS#, CAS#, and WE# as well as the plurality of chip select signals. Each chip enable circuit 206 may receive RAS#, CAS#, and WE# command signals as well as a corresponding chip select signal.

Chip enable circuits 206 may compare received command signals to determine if a valid command has been received by master memory unit 102. In the event that a valid command has been received and a chip enable circuit 206 has received a chip select signal in an active state, the corresponding chip enable circuit 206 may couple the chip select signal onto a corresponding signal line of the interconnect bus 110, thereby enabling the memory unit corresponding to the active chip select signal. Some commands, however, may be valid but any active state chip select signals also received may not be provided to any of the memory units. For example, if a command is decoded as a NoOp (i.e., no operation), chip enable circuit 206 may not provide an active chip select signal on the corresponding signal lines on interconnect bus 110 even if a chip enable circuit 206 has received a chip select signal in an active state. In at least one embodiment, preventing active state chip select signals received by the chip enable circuits 206 from being coupled onto interconnect bus 110 may be done by utilizing a transistor, for example, such as in cases using a transistor as a switch. However, other methods that may be used will be apparent to those skilled in the art.

Command latch decoder 204 may decode a command received from input path 202 to generate a decoded command. Command latch decoder 204 may further be configured to receive the plurality of chip select signals and determine whether memory 100 is in a deselect condition, indicating that all chip select signals are inactive. If memory 100 is not in a deselect condition, the decoded command may be coupled to the interconnect bus 110 where an enabled memory unit may read and execute the decoded command. If the command latch decoder 204 detects a deselect condition, commands may be prevented from being coupled onto interconnect bus 110. In some embodiments, preventing the coupling of commands to interconnect bus 110 in this manner may be done using transistor logic. However, other methods that may be used will be apparent to those skilled in the art.

Command latch decoder 204 and/or the chip enable circuits 206 may also generate internal signals that are derived from the command signals each may receive. In at least one embodiment, received signals may be shifted and/or truncated and provided to interconnect bus 110. This may improve relative timing between signals provided to master memory unit 102 and slave memory units 104 a-c. For example, by providing a greater timing margin for the chip select signals relative to the command signals, more robust operation may be provided. In a number of embodiments, functionality of chip enable circuits 206 and command latch decoder 204 may be combined. For example, the logical functionality of chip enable circuits 206 and command latch decoder 204 could be implemented in master memory unit 102 as a single logic circuit. It will be appreciated by those ordinarily skilled in the art that various implementations may also be used without departing from the scope of the present invention.

As noted above, command latch decoder 204 may be configured to receive all of the chip select signals received by memory 100 (FIG. 1). FIG. 3 illustrates the command latch decoder 204 according to an embodiment of the invention having four memory units. Chip select signals CS0# and CS1# may be combined using NOR logic gate 304 and chip select signals CS2# and CS3# may also be combined using NOR logic gate 308. Command latch decoder 204 may include a logic circuit 302 coupled to the NOR gates 304, 308 that is configured to decode command signals RAS#, CAS#, and WE# to generate a decoded command as well as detect a deselect condition when all chip select signals have an inactive state based on the output of the NOR gates. Unless a deselect condition is detected, any decoded command will be output on global command bus 207. In the event that all chip select signals are in an inactive state (i.e., a deselect condition), logic circuit 302 will not provide the output of the command latch decoder 204 to interconnect bus 110 regardless of whether a valid command is decoded or not. It will be appreciated by those in the art that other control logic implementations, such as a command latch decoder absent NOR gates, may also be utilized without departing from the scope of the present invention. It may further be appreciated that other logical states may represent a deselect condition and the embodiment described is in no way limiting.

FIG. 4 illustrates a chip enable circuit 206 according to an embodiment of the invention. The chip enable circuit 206 receives a corresponding chip select signal and command signals RAS#, CAS#, and WE#. A NOR gate 408 may receive the corresponding chip select signal and the RAS# command signal. A NOR gate 412 may receive the CAS#, RAS# and WE# command signals. The output from both NOR gates 408, 412 may be coupled to logic circuit included in chip enable circuit 206. Logic circuit 404 may determine from the state of the NOR gate outputs if the current command is a NoOp. In that instance, the chip enable circuit 206 does not provide the corresponding chip select signal to latched chip select bus 209. Where the current command is not a NoOp command, the chip select signal may be provided to master interconnect 208 and subsequently provided to interconnect bus 110. It will be appreciated by those in the art that other control logic implementations, such as a chip enable circuit 206 absent NOR gates, may also be utilized without departing from the present invention. It may further be appreciated that other logical states may represent a deselect condition and the embodiment described is in no way limiting.

FIGS. 5A and 5B further illustrate control logic involved with NoOp and deselect conditions in memory 100. FIG. 5A depicts a control logic table according to an embodiment of the invention. Each chip enable circuit 206 may receive a row address select signal, a column address signal, a write enable signal, and a corresponding chip select signal. In the case where RAS#, CAS# and WE# all have an inactive state, this is decoded to a NoOp command. Such a command may cause chip enable circuit 206 to not provide the chip select signals to interconnect bus 110 (FIG. 2). As a result, the chip select signals are considered as “don't-cares” (illustrated in FIG. 5A as “X”) as the chip select signals are not coupled to interconnect bus 110 and no memory unit is enabled to execute a command.

This may provide the benefit of reducing the number of state changes required on interconnect bus 110 thereby reducing power consumption. Additionally, erroneous memory unit operation caused by mismatched timing of the signals on the interconnect bus 110 may be reduced. For example, due to inherent signal propagation delay on the interconnect bus 110, chip select signals may not be synchronized with command signals by the time the chip select signals and command signals are received by the respective memory units on interconnect bus 110. In severe cases of timing skew between, for example, the chip select signals and the command signals, an active chip select signal that is originally associated with a NoOp command may inadvertently enable the corresponding memory unit to read a later valid command propagating on the interconnect bus 110 intended for another memory unit. Thus, errors caused by improperly timed chip select and command signals provided to the memory units on interconnect bus 110 may also be reduced by applying the control logic table of FIG. 5A. That is, rather than having a memory unit inadvertently enabled by an active chip select signal associated with a NoOp command, the receipt of the NoOp command causes the chip enable circuit 206 to prevent coupling any active chip select signal to the interconnect bus 110 to the memory units.

A control logic table according to an embodiment of the invention is shown in

FIG. 5B. Because the command latch decoder 204 receives each chip select signal, as noted above, deselect conditions may be detected. In the event that all chip select signals have an inactive state, command signals, such as RAS#, CAS#, and WE# become “don't-cares” (shown in FIG. 5B as “X”) as these signals are not provided over interconnect bus 110 by the command latch decoder 204. By not providing the command signals, fewer state changes are required on interconnect bus 110, reducing power consumption. Moreover, because some commands may require multiple clock cycles for execution, in the event that a memory unit improperly registers a command on interconnect bus 110 not intended for any of the memory units (i.e., during the deselect condition), any valid subsequent commands may be ignored if the memory unit is still executing the improperly registered command. For example, an active chip select signal associated with a valid command provided after the deselect condition may inadvertently enable the corresponding memory unit to read the previous command provided during the deselect condition, which may still be propagating on the interconnect bus 110 at the time the active chip select signal would have been provided by the command latch decoder 204. Thus, by not providing commands to the interconnect bus 110, for example, when a deselect condition occurs, errors incurred due to ignored valid commands may be reduced.

As previously described, master memory unit 102 and slave memory units 104 a-c may be configured to read command signals from interconnect bus 110 at the time a corresponding chip select signal becomes active. A greater timing margin available for the chip select signals relative to the command signals may provide more robust operation of a memory, for example, memory 100. FIG. 6 shows a timing diagram according to one embodiment of the invention providing greater timing margin for the chip select signal. A chip select signal CS0# corresponding to the master memory unit 102 has a width smaller than a width of a command provided on interconnect bus 110. The chip select signal is also shifted such that the rising edge of command signal 601 is earlier than the rising edge of the chip select signal 602, resulting in delay 605. Additionally, the falling edge of the chip select signal 602 occurs before the falling edge of the command signal 601, resulting in delay 607. Thus, the chip select signal CS0# should not become active when the corresponding decoded command signal is not also active on the interconnect bus 110. This may be accomplished with signal truncation and/or signal shifting, or other methods known in the art. For example, in one embodiment, chip select signals may be truncated using control logic in the chip enable circuits 206 or in master interconnect 208. In another embodiment, chip select signals may be truncated using rising and/or falling edges of a clock signal. In yet another embodiment, chip select signals may be delayed using gate delays. It will be appreciated by those ordinarily skilled in the art that various implementations may also be used without departing from the scope of the present invention.

As noted above, chip select signals may be truncated or delayed to increase available timing margins for the chip select signals relative to the command signals. FIG. 7 illustrates a chip enable circuit 701 having a chip select feedback circuit 702 according to an embodiment of the invention. Chip select feedback circuit 702 may have an output inverter 714 and a feedback inverter 716. A NAND gate 722 may receive a delayed clock signal ClkDly, a reset signal, and the output of feedback inverter 716. A NAND gate 724 may receive an output of the NAND gate 722 in addition to an inverted clock signal, ClkF. The output of the NAND gate 724 may be coupled to the gate of a transistor 730. Additionally, a NOR gate 726 may receive a clock signal CLK and the output of the NAND gate 722. The output of the NOR gate 726 may be coupled to the gate of transistor 732.

In operation, if chip enable circuit 701 has determined that a received command is not a NoOp and that the memory corresponding to chip enable circuit 701 is to be enabled, output inverter 714 and feedback inverter 716 may transition to an active state. The transition of output inverter 714 to an active state may result in the enablement of the chip select signal corresponding to chip enable circuit 701 on latched chip select bus 209. When inverted clock signal ClkF is in an active state, a feedback path, consisting of feedback inverter 716, NAND gate 722, NOR gate 726, and transistor 732, may be enabled and cause the output of output inverter 714 to remain in an active state until the delayed clock signal ClkDly also transitions to an inactive state. When this occurs, the feedback path may be disabled and cause the output of NAND gate 722 to deactivate the output of NOR gate 726, in turn causing transistor 732 to turn off. Delayed clock signal ClkDly transitioning to an inactive may also cause NAND gate 724 to activate transistor 730, thereby causing the output of output inverter 714 to transition to an inactive state.

As a result of inputting delayed clock signal ClkDly into NAND gate 722, the period of time in which the output of output inverter 714 is in an active state may be truncated. The amount of truncation may be any length up to a full clock cycle. For example, in at least one embodiment, truncation may be approximately half the clock period. In another embodiment, truncation may be a quarter clock cycle. It will be appreciated by those in the art that other control logic implementations may also be utilized without departing from the scope of the present invention.

FIG. 8 illustrates a front perspective view of a memory 100. As described above, slave memory units 104 a-c may be stacked on master memory unit 102. In at least one embodiment, master memory unit 102 may be located at the bottom position of the memory unit stack. In other embodiments, master memory unit may be on top of the stack or placed between slave memory units 104 a-c. Moreover, interconnects 810 a-d may allow master memory unit 102 and slave memory units 104 a-c to exchange data and commands on common busses. For example, as shown in FIG. 8, four interconnects may be used. It will be appreciated by those having skill in the art, however, that any greater or lesser number of interconnects may be used.

Additionally, master memory unit 102 and slave memory units 104 a-c may be substantially similar. In one embodiment, interconnects 810 a-d may extend through master memory unit 102 and slave memory units 104 a-c at the same relative locations of each memory unit. Additionally, in another embodiment, control logic 820 in master memory unit 102 may be reproduced in each slave memory unit 104 a-c such that any of the memory units may operate as the master memory unit of a stack if configured to do so.

From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims. 

What is claimed is:
 1. An apparatus comprising: a first memory unit including a first array of memory cells, the first memory unit configured to receive command information and chip select information; and a second memory unit including a second array of memory cells, the second memory unit coupled to the first memory unit, the first memory unit configured to access data stored in the first array of memory cells responsive to the command information when the chip select information designates the first memory unit, and further configured to cause the second memory unit to access data stored in the second array of memory cells responsive to the command information when the chip select information designates the second memory unit.
 2. The apparatus of claim 1, wherein: the first memory unit includes control logic configured to decode the command information to produce decoded command information; and the second memory unit is configured to receive the decoded command information and execute the decoded command information to access the second array of memory cells when the chip select information designates the second memory unit.
 3. The apparatus of claim 2, wherein the second memory unit does not receive the decoded command information when the chip select information designates the first memory unit.
 4. The apparatus of claim 2, wherein the second memory unit does not receive the chip select information designating the second memory unit when the decoded command is a No Operation command.
 5. The apparatus of claim 1, wherein the chip select information designating the second memory unit is sent to the second memory unit after the command information is sent to the second memory unit.
 6. The apparatus of claim 1, wherein the first and second memory units are configured in a stack.
 7. The apparatus of claim 6, wherein the first and second memory units are placed together into a single package.
 8. The apparatus of claim 6, wherein the first and second memory units are interconnected by through silicon vias.
 9. The apparatus of claim 2, wherein the first and second memory units are configured in a stack and are interconnected by through silicon vias, and wherein the decoded command information is transferred from the first memory unit to the second memory unit by way of the through silicon vias.
 10. The apparatus of claim 9, wherein the data stored in the second array of memory cells are transferred through the first memory unit by way of the through silicon vias.
 11. The apparatus of claim 1, wherein the first and second memory units are identical.
 12. An apparatus comprising: first and second memory units placed together into a single package, the first and second memory units including a first array of memory cells and a second array of memory cells, respectively; and an external node coupled to the first memory unit, wherein the first memory unit includes logic, the logic configured to receive command information and chip select information via the external node, decode the command information to produce a decoded command information, and provide active first and second chip select information, the first memory unit being enabled to access data stored in the first array of memory cells according to the decoded command information when the logic provides the active first chip select information, and wherein the second memory unit is configured to receive the decoded command information from the logic and access data stored in the second array of memory cells according to the decoded command information when the logic provides the active second chip select information.
 13. The apparatus of claim 12, wherein the logic does not provide the second memory unit with the decoded command information when the second chip select information is in an inactive state.
 14. The apparatus of claim 12, wherein the logic does not provide the second memory unit with the active second chip select information when the decoded command information is a No Operation command.
 15. The apparatus of claim 12, wherein the active second chip select information is provided to the second memory unit after the command information is provided to the second memory unit.
 16. The apparatus of claim 12, wherein the first and second memory units are interconnected with through silicon vias.
 17. The apparatus of claim 12, wherein the first and second memory units are stacked and are interconnected by through silicon vias, and wherein the decoded command information is transferred from the external node through the first memory unit to the second memory unit by way of the through silicon vias.
 18. The apparatus of claim 17, wherein the data stored in the second array of memory cells are transferred through the first memory unit to the external node by way of the through silicon vias.
 19. An apparatus comprising: a first memory unit including a first array of memory cells; and a second memory unit including a second array of memory cells, the second memory unit coupled to the first memory through a control bus and a data bus, wherein the first memory unit is configured to receive command information and chip select information and decode the command information to provide decoded command information, the first memory unit enabled to execute the decoded command information to access data stored in the first array of memory cells based on whether the chip select information designates the first memory unit; and wherein the second memory unit is configured to be enabled to execute the decoded command information provided by the first memory unit through the control bus to access data stored in the second array of memory cells, and wherein the second memory unit is configured to provide the data stored in the second array of memory cells to the data bus based on whether the second memory unit receives the chip select information designating the second memory unit, the chip select information received through the control bus.
 20. The apparatus of claim 19, wherein the first memory unit does not provide the second memory unit with the decoded command information when the chip select information designates the first memory unit. 